Dynamic reconfigurable processor is a new processor which is advantageous over conventional single-core processors, dedicated chips and field programmable logic arrays, and is a future direction for developing circuit structures.
Firstly, the dynamic reconfigurable processor often contains a plurality of arithmetic logic units in large quantities which are also called many-core array. The many-core array has a routing unit with high flexibility in the interior thereof, so as to realize diversified interconnections between the arithmetic logic units. Therefore, the many-core array connected by the routing unit can process data with a high speed, which is advantageous over the traditional single core and less-core processors in performance. Meanwhile, the multi-core array is also advantageous over the cured dedicated circuits in flexibility.
The previous static reconfigurable circuit only programs circuit function before the operation of the circuit and initializes the circuit, without changing the circuit function. Compared to the traditional static reconfigurable circuit (such as field programmable logic array), the dynamic reconfigurable processor has dynamic characteristics, i.e. being capable of dynamically switching circuit functions during the operation of the circuit. In this way, the circuit scale is reduced, because the circuit structure has changed from full mapping to block mapping, and dynamic switching may be performed between the blocks.
However, dynamic switching design of the current dynamic reconfigurable processor has at least the following problems:
1) a large quantity of configuration information resulting in increases of the configuration time and capacity of the configuration memory;
2) an increase of the configuration power due to the frequent switching configuration information in the dynamic reconfigurable processor;
3) being not capable of switching configuration of one processing unit without keeping other processing units in original configurations. In other words, during the configuration of the reconfigurable processor array, as long as the function of one processing unit is changed, the entire array is required to be reconfigured. That is to say, a large quantity of blind configurations need to be performed.